View ADUCM320_9015206.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

precision analog microcontroller, 14 - bit analog input/output with mdio interface, arm cortex - m3 data sheet ADUCM320 rev. c document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may r esult from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2014 C 2015 analog devices, inc. all rights reserved. techni cal support www.analog.com features analog input/output multichannel, 14 - bit, 1 msps analog - to - digital converter ( adc ) up to 16 adc input channels 0 v to vref analog input range fully differential and single - ended modes av dd and iov dd monitor s 12- bit voltage output digital - to - anal og converters (vdacs) 8 vdacs with a range of 0 v to 2.5 v or av dd outputs 12 - bit current output dacs ( idacs ) 4 idacs with a range of 0 ma to 150 ma outputs voltage comparator microcontroller arm ? cortex ? - m 3 processor, 32 - bit risc architecture serial wire port supports code download and debug clocking options 80 mhz phase - locked loop ( pll ) with programmable divider trimmed on - chip oscillator ( 3 %) external 16 mhz crystal option external clock source up to 80 mhz memory 2 128 kb independent f lash/ee memo ries 10,000 cycle f lash/ee endurance 20 - year f lash/ee retention 32 kb sram software triggered in - circuit reprogrammability via management data input/output ( mdio ) on - chip peripherals mdio slave up to 4 mhz 2 i 2 c, 2 spi, uart multiple general - purpo se input/output ( gpio ) pins : 3.6 v compliant 7 1.2 v compatible when used for mdio 32 - element programmable logic array (pla ) 3 general - purpose timers wake - up timer watchdog timer 16 - bit pulse width modulator ( pwm ) power supply range: 2.9 v to 3.6 v , and 1.8 v to 2.5 v for idacs flexible operating modes for low power applications packages and temperature range 6 mm 6mm , 96- ball csp_ bga package fully specified for ? 40 c to +10 5c ambient operation tools low cost quickstart ? development system full third p arty support applications optical networking
ADUCM320* product page quick links last content update: 08/30/2016 comparable parts view a parametric search of comparable parts evaluation kits ? ADUCM320 evaluation board documentation application notes ? an-1310: flash programming via mdio?protocol type 8 ? an-1322: ADUCM320 code execution speed data sheet ? ADUCM320: precision analog microcontroller, 14-bit analog i/o with mdio interface, arm cortex-m3 data sheet user guides ? ug-498: ADUCM320 hardware reference manual ? ug-692: ADUCM320 development systems getting started tutorial design resources ? ADUCM320 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all ADUCM320 engineerzone discussions sample and buy visit the product page to see pricing options technical support submit a technical question or find your regional support number * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet. this content may be frequently modified.
ADUCM320 da ta sheet rev. c | pa ge 2 of 30 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 revision history ............................................................................... 2 functional block diagram .............................................................. 3 general description ......................................................................... 4 specifications ..................................................................................... 5 microcontroller electrical specifications .................................. 5 timing specifications ................................................................ 15 absolute maximum ratings ..................................................... 21 esd caution ................................................................................ 21 pin configuration and function descriptions ........................... 22 typical performance characteristics ........................................... 27 recommended circu it and component values ........................ 28 packaging and ordering information ......................................... 30 outline dimensions ................................................................... 30 ordering guide .......................................................................... 30 revision history 10 /15 rev. b to rev. c change to features section ............................................................. 1 added table 2 ; renumbered sequentially .................................. 10 changes to table 7 and figure 5 ................................................... 18 changes to table 8 a nd figure 6 ................................................... 19 change to table 10 ......................................................................... 21 changes to figure 14 ...................................................................... 27 changes to ordering guide .......................................................... 30 3/15 rev. a to rev. b changes to table 1 ............................................................................ 7 changes to t shd and t psu parameters, table 3 .............................. 10 1 1 /14 rev . 0 to rev. a changes to figure 1 .......................................................................... 3 changes to general descripti on .................................................... 4 changes to table 1 ............................................................................ 5 added timing specifications section .......................................... 10 add ed figure 2 ; renumbered sequentially ................................ 1 0 added figure 3 ................................................................................ 1 1 added figure 4 ................................................................................ 1 2 added figure 5 ................................................................................ 1 3 added figure 6 and figure 7 ......................................................... 1 4 changes to a bsolute m aximum r atings s ection ....................... 1 5 changes to p i n c 3 and pin a 11 descriptions ............................ 17 changes to ordering guide .......................................................... 2 4 6 / 14 revision 0: initial version
data sheet ADUCM320 rev. c | page 3 of 30 functional block dia gram figure 1. memory 2 128kb flash 32kb sram arm cortex m3 processor mux reset ain0 ain5 ain6 ain15 buf_vref2v5 vdac7 idac0 ADUCM320 pvddx agndx iovddx iogndx genera l purpose i/o ports swdio swclk gpio ports uart 2 spi 2 i 2 c ext irqs mdio pla internal channels: temperature, av dd , iov dd 2.5v band gap dma nvic reset system serial wire clock system 32.768khz 16mhz osc 80mhz pll 3 gp timer wd timer w ake-u p timer pwm vdac idac3 14-bit sar adc idac idac compa- rator xtalo xtali eclkin pgnd avddx dgndx pwm0 t o pwm6 1.8 v ldo 12272-001 vdac0 vdac
ADUCM320 da ta sheet rev. c | pa ge 4 of 30 general description the ADUCM320 is a fully integrated single package device that incorporates high performance analog peripherals together with digital peripherals controlled by an 80 mhz arm cortex - m 3 processor and integral flash for code and data. the adc on t he ADUCM320 provides 14 - bit , 1 msps data acquisition on up to 16 input pins that can be programmed for single - ended or differential operation . the voltage at the idac output pins can also be m easured by the adc , which is useful for controlling the power consumption of the current dacs. a dditionally , chip temperature and supply voltages can be measured. the adc input voltage is 0 v to v ref . a sequencer is provided , whi ch allows a user to select a set of adc channels to be measured in sequence without software in volvement during the sequence. the sequence can optionally repeat automatically at a user selectable rate. up to eight v dacs are provided with output ranges that are programmable to one of two voltage ranges. four i dac sources are provided. the output currents are programmable with ranges of 0 ma to 150 ma. a low drift band gap reference and voltage comparator completes the analog input peripheral set. t he ADUCM320 can be configured so that the digital and a nalog outputs will retain their output voltages and currents through a watchd og or software reset sequence. thus , a product can remain functional even while the ADUCM320 is resetting itself. the ADUCM320 has a low power arm cortex - m3 processor and a 32 - bit risc machine that offers up to 100 mips p eak performance. also integrated on chip are 2 128 kb f lash/ee memory and 32 kb of sram. the flash comprises two separate 128 kb blocks supporting execution from one flash block and simultaneous writing/erasing of the other flash block. the ADUCM320 operates from an on - chip oscillator or a 16 mhz external crystal and a pll at 80 mhz. this clock can optionally be divided down to reduce current consumption. additional low power modes can be se t via software. in normal operating mode , the ADUCM320 digital core consumes about 300 a per mhz. the device includes an mdio interface capable of operating at up to 4 mhz. the capability to simultaneously execute from one flash block and write/erase the other flash block makes the ADUCM320 ideal for 10g, 40g , and 100g optical applications. user programming is eased by incorporat ing ph ya dr an d devadd hardware comparators. in addition , the nonerasable kernel code plus flags in user flash provide assistance by allow ing user code to robustly switch between the two blocks of user flash code and data spaces . the ADUCM320 integrates a range of on - chip peripherals that can be configured under software control , as required in the appli - cation . these peripherals include 1 ua rt, 2 i 2 c , and 2 spi s erial input/output commun ication controllers, gpio, 32 - element programmable logic array, 3 general - purpose timers , plus a wake - up timer and system watchdog timer. a 16 - bit pwm with seven output channels is al so provided. gpio pins on the device power up in high impedance input mod e . in output mode , the software choose s between open - drain mode and push - pull mode. the pull - up resistor s can be disabled and enabled in software. in gpio output mode , the inputs can remain enabled to monitor the pins. the gpio pins can also be programmed to han dle digital or analog peripheral signals , in which case the pin characteristics are matched to the specific requirement. a large support ecosystem is available for the a rm cortex - m3 processor to ease product development of the ADUCM320 . access is via the arm serial wire debug port (sw - dp). on - chip factory firmware supports in - cir cuit serial download via mdio. these features are incorporated into a low cost quickstart development system su pporting this precision analog microcontroller family.
data sheet ADUCM320 rev. c | page 5 of 30 specifications microcontroller elec trical specification s av dd = iov dd = vdd1 = 2.9 v to 3.6 v ( s ee figure 14) m ax imum difference between supplies = 0.3 v, v r ef = 2.5 v internal reference, f core = 80 mhz, t a = ?40c to +85c, unless otherwise noted. pvdd x for idacs = 1.8 v to 2.5 v . power - up sequence must be vdd1, iovdd x , av dd x , and then pvdd x , but no dela ys in the sequence are required . table 1 . parameter symbol min typ max unit test conditions/comments adc basic specifications single - ended mode , unless otherwise stated adc power - up time 5 s data rate f sample 1 msps dc accuracy 1 14 bits 1 lsb = 2.5 v/2 14 resolution 1 16 bits number of data bits integral nonlinearity inl 1 .75 lsb 2.5 v internal reference ; 1 lsb = 2.5 v/2 14 1.75 lsb 2.5 v external reference ; 1 lsb = 2.5 v/2 14 differential nonlinearity dnl ?0.99 0. 75 +1 lsb 2.5 v internal reference ; 1 lsb = 2.5 v/2 14 0.75 lsb 2.5 v external reference ; 1 lsb = 2.5 v/2 14 dc code distribution 3 lsb adc input 1.25 v ; 1 lsb = 2.5 v/ 2 14 adc endpoint errors offset error input buffer off 200 v drift 1 ? 2.25 + 1.2 v/c using 2.5 v external reference input buffer on ?250 v drift 1 ? 2.6 + 2 v/c using 2.5 v external reference ma tch 1 lsb matching compared to ain8 full - scale error input buffer off 400 v gain drift 1 ? 4 + 2 v /c full - scale error drift minus offset error drift input buffer on ?350 v gain d rift 1 ? 4.5 + 3 v /c full - scale error drift minus offset error drift match 1 lsb adc dynamic performance f in 2 h sine wae, f sample 100 sps input filter 1 , 2 nf signal - to - nois e ratio snr inclues istortion an noise coponents input buffer disale 0 b enale 4 b total haronic distortion thd input buffer disale b enale 3 b pea haronic or spurious noise b channel - to - channel crosstal 0 b measure on aacent channels adc input input uffer not enale input voltage ranges single - ene moe 1 agnd4 vref differential moe 1 vref vref v voltage etween ifferential pins copliance 1 agnd4 avdd4 coon moe 1 0 1 v
ADUCM320 data sheet rev. c | page 6 of 30 parameter symbol min typ max un it test conditions/comments leakage current ain0 to ain4, ain6 to ain15 1.5 na ain5 20 na pin shared with comparator input current 9 a/v at 1 msps; buffer off 6 a/v 800 ksps; buffer off 4 a/v 500 ksps; buffer off; adccnvc[25:16] = 0x1e input capacitance 20 pf during adc acquisition adc input buffer 2 when enabled by software voltage compliance 1 0.15 2.5 v reduced accuracy below 0.15 v input current 100 na v in = 0.15 v to 2.5 v, adc converting on-chip voltage reference 2.51 v 0.47 f from vref_1v2 to agnd4; reference is measured with all adcs, vdacs, and idacs enabled accuracy 5 mv t a = 25c reference temperature coefficient 1 ?34 ?15 +4 ppm/c power supply rejection ratio psrr 60 db internal v ref power-on time 50 ms external reference input range 1 1.8 2.5 v adc input current 200 a buffered reffernce output output voltage 2.504 v accuracy 8 mv t a = 25c, load = 1.2 ma reference temperature coefficient 1 ?55 ?5 +40 v/c 100 nf from buf_vref2v5 to agnd4 output impedance 10 t a = 25c load current 1 1.2 ma vdac channel specifications r l = 5 k, c l = 100 pf 3 dc accuracy 1 12 bits 1 lsb = 2.5 v/2 12 resolution 1 12 bits number of data bits relative accuracy 4 inl 4 lsb 1 lsb = 2.5 v/2 12 differential nonlinearity 4 dnl ?0.99 +1 lsb guaranteed monotonic, 1 lsb = 2.5 v/2 12 offset error 3 15 mv 2.5 v internal reference, dac output code 0 drift 13 v/c gain error 5 0.3 0.85 % 0 v to internal v ref range 0.4 1 % 0 v to avdd range drift 6.5 ppm/c excluding reference drift mismatch 0.1 % % of full scale on dac0 analog outputs output voltage range 1 1 0.15 2.5 v output voltage range 2 1 0.15 avddx? 0.15 v output impedance 2 dac ac characteristics output settling time 10 s settled to 1 lsb glitch energy 20 nv-sec 1 lsb change when the maximum number of bits changes simultaneously in the dacxdat register idac channel specifications resolution 1 14 bits combination of overlapping 11 bits and 5 bits full-scale output 1 150 ma supply voltage each channel 1 1.8 2.5 v separate pvddx supply for each channel output compliance range idac0, idac1 0.4 pvddx ? 400 mv v see figure 11 idac2, idac3 0.4 pvddx ? 250 mv v see figure 11
data sheet ADUCM320 rev. c | page 7 of 30 parameter symbol min typ max unit test conditions/comments full - scale error idac set to 85% of full scale idac0, idac1 0.75 % 25c to 105 c range 3.5 % ?40c to +105c range idac2, idac3 0.75 % ?40c to +105c range full - scale error drift idac0, idac1 internal v ref ?40c to +85c 25 a/c 25c to 85c 5 a/c idac2, idac3 2 a/c internal v ref integral nonlinearity inl 3 6 lsb 1 lsb = 150 ma/2 11 differential nonlinearity dnl ?0.99 +1 .5 lsb guaranteed 11 - bit monotonic, 1 lsb = 150 ma/2 11 zero - scale error 50 a zero - scale error drift idac0, idac1 300 na/c idac2, idac3 800 na/ c noise current 2 a idacxcon[5:2] = 0 pull - down current ?220 ?165 ?100 a when enabled settling time idacxcon[5:2] = 0 to 0.1% 100 s 4 ma change from midscale to 1% 50 s 4 ma change from midscale full scale to 0 ma 20 s pu ll - down enabled overheat shutdown 135 c junction temperature pvdd acpsrr idacxcon[5:2] = 0 100 hz 51 db 1 khz 45 db 10 khz 25 db 100 khz 10 db comparator input offset voltage 10 mv bias current 1 na voltage range 1 agndx avddx C 1.2 v capacitance 7 pf hysteresis 1 8.5 15 mv when enabled in software response time 7 s afecomp[2:1] = 0 tempe rature sensor indicates die temperature, see figure 9 resolution 0.5 c when pr ecision calibrated by the user 6 accuracy 1 1.34 1.43 v adc measured voltage for temperature senso r channel without calibration, t = 25 c power - on reset por 2.85 2.9 v external reset minimum pulse width 1 1.5 s minimum pulse width required on external reset pin to trigger a reset sequence w atchdog timer wdt timeout period 32 sec default at power - up flash/ee memory endurance 1 10,000 cycles data retention 1 20 years t j = 85c
ADUCM320 data sheet rev. c | pa ge 8 of 30 parameter symbol min typ max unit test conditions/comments digital inputs input leakage current logic 1 gpio 1 na v ih = v dd , pull - up resistor disabled logic 0 gpio 10 na v il = 0 v, pull - up resistor disabled prtaddrx input leakage current 16 a v in = 0 to 1.8 v, due to weak p ull - up resistors to 1.8 v input voltage 0.84 1.5 v external resistor 91 k? 1% to ground, r ange for cfp msa high 1 input capacitance, all pins except mck , mdio , prtaddr x, and xtal x 10 pf input capac itance mck, prtaddrx 6.5 pf mdio 8.5 pf pin capacitance xtali 5 pf xtalo 5 pf logic inputs gpio input voltage low v inl 0.25 iovddx v high v inh 0.58 iovddx v mdio prtaddrx input voltage low v inl 0.36 v high v inh 0.84 v mck, mdio input voltage setup time 10 ns; hold time 10 ns; mck/mdio low v inl 0.36 v high v inh 0.84 v xtali input voltage low v inl 1.1 v high v inh 1.7 v pull - u p current 30 120 a v in = 0 v, see figure 10 pull - d own curr ent 30 100 a v in = 3.3 v, see figure 10 logic outputs all digital outputs excluding xtalo gpio output voltage 7 high v oh iovddx ? 0.4 v i source = 2 m a low v ol 0.4 v i sink = 2 ma gpio short - ci rcuit current 1 11 ma see figure 13 mdio output voltage high v oh 1.0 v i source = 4 m a low v ol 0.2 v i sink = 4 m a delay time 100 ns mck to mdio out oscillators internal system oscillator 16 mhz accuracy 0.5 3 % system pll 80 mhz main system clock external crystal oscillator 16 mhz can be selected in place of internal oscillator 32 khz internal oscillator 32.768 khz use for watchdog accuracy 5 20 % external clock 0.05 80 mhz can be selected in place of pll start - up time processor clock = 80 mhz at power - on 40 ms por to first user code execution after other reset 1.5 ms reset to first user code execution from all power - down modes 1.25 s
data sheet ADUCM320 rev. c | page 9 of 30 parameter symbol min typ max un it test conditions/comments programmable logic array pla propagation delay pin 17 ns from input pin to output pin element 1.5 ns per pla cell external interrupts pulse width 1 level triggered 7 ns edge triggered 1 ns power requirements 8 power supply voltage range avddx to agndx and iovddx to dgndx 1 2.9 3.3 3.6 v analog power supply currents avddx current 6.3 ma analog peripherals in idle mode digital power supply current iovddx current in normal mode 4 ma all gpio pull-up resistors enabled vddx current normal mode 9 29 ma cd = 0 (80 mhz clock) executing typical code 20 ma cd = 1 executing typical code 10 ma cd = 7 executing typical code core_sleep mode 9 16 ma sys_sleep mode 9 8 ma hibernate mode 9 6.6 ma additional power supply currents adc 4.1 ma continuously converting at 100 ksps adc input buffer 4.0 ma both buffers enabled idac 16.5 ma excluding load current dac 340 a per powered up dac, excluding load current total supply current 35 40 45 ma vdd1, iovddx, avddx connected together; condition when entering user code: peripheral clocks on, peripherals idle, no load currents thermal performance impedance junction to ambient 45 c/w jedec 2s2p 1 these numbers are not production tested but are guaranteed by design and/or characterization data at production release. 2 enabling the input buffer changes the adc input characteristics as described in this subsection. 3 the data in this section a lso applies for a load of r l = 1 k and c l = 100 pf to gnd but only for 0 v to 2.5 v. however, this is not production tested. 4 dac linearity is calcul ated using a reduced co de range of 100 to 3900. 5 dac gain error is calculated using a reduced code range of 100 to an internal 2.5 v v ref . 6 due to self heating, internal temperature measurements cannot be used to predict external temperatures. this value is only relevant after user calibration and only for internal and external conditions identical to those at calibration. 7 the average current from all gpio pins must not exceed 3 ma per pin. 8 power figures exclude any load cu rrents to external circuits. 9 see the ADUCM320 reference manual, how to set up and use the ADUCM320 .
ADUCM320 data sheet rev. c | pa ge 10 of 30 a v dd = iov dd = vdd1 = 2.9 v to 3.6 v maximum differ ence between supplies = 0.3 v, vref = 2.5 v internal reference, f core = 80 mhz, t a = ?4 0c to +105c, unless otherwise noted. pvddx for idacs = 1.8 v to 2.5 v. power - up sequence must be vdd1, iovddx, avddx, and then pvddx , but no delays in the sequence ar e required. table 2 . parameter symbol min typ max unit test conditions/comments adc basic specifications single - ended mode, unless otherwise stated adc power - up time 5 s data rate f sample 1 msps dc accuracy 1 14 bits 1 lsb = 2.5 v/2 14 resolution 1 16 bits number of data bits integral nonlinearity inl 1.75 lsb 2.5 v internal reference; 1 lsb = 2.5 v/2 14 1.75 lsb 2.5 v external reference; 1 lsb = 2.5 v/ 2 14 differential nonlinearity dnl ?0.9 9 0.75 +1 .5 lsb 2.5 v internal reference; 1 lsb = 2.5 v/2 14 0.75 lsb 2.5 v external reference; 1 lsb = 2.5 v/2 14 dc code distribution 3 lsb adc input 1.25 v; 1 lsb = 2.5 v/2 14 adc endpoint errors o ffset error input buffer off 200 v drift 1 ?2.25 +1.2 v/c using 2.5 v external reference input buffer on ?250 v drift 1 ?3 +2 v/c using 2.5 v external reference match 1 lsb matching compared to ain8 full - scale error input buffer off 400 v gain drift 1 ?4.3 +2 v/c full - scale error drift minus offset error drift input buffer on ?350 v gain drift 1 ?4.5 +3 v/c full - scale error drift minus offset error drift match 1 lsb adc dynamic performance f in 2 h sine wae, f sample 100 sps inpu t filter 1 , 2 nf signal - to - noise ratio snr inclues istortion an noise coponents input buffer disale 0 b enale 4 b total haronic distortion thd input buffer disale b enale 3 b pea haronic or spurious noise b channel - to - channel crosstal 0 b measure on aacent channels adc input input uffer not enale input voltage ranges single - ene moe 1 agnd4 vref differential moe 1 vref vref v voltage etween ifferential pins copliance 1 agnd4 avdd4 coon moe 1 0 1 v
data sheet ADUCM320 rev. c | page 11 of 30 parameter symbol min typ max un it test conditions/comments leakage current ain0 to ain4, ain6 to ain15 1.5 na ain5 20 na pin shared with comparator input current 9 a/v at 1 msps; buffer off 6 a/v 800 ksps; buffer off 4 a/v 500 ksps; buffer off; adccnvc[25:16] = 0x1e input capacitance 20 pf during adc acquisition adc input buffer 2 when enabled by software voltage compliance 1 0.15 2.5 v reduced accuracy below 0.15 v input current 100 na v in = 0.15 v to 2.5 v, adc converting on-chip voltage reference 2.51 v 0.47 f from vref_1v2 to agnd4; reference is measured with all adcs, vdacs, and idacs enabled accuracy 5 mv t a = 25c reference temperature coefficient 1 ?34 ?15 +4 ppm/c power supply rejection ratio psrr 60 db internal v ref power-on time 50 ms external reference input range 1 1.8 2.5 v adc input current 200 a buffered reffernce output output voltage 2.504 v accuracy 8 mv t a = 25c, load = 1.2 ma reference temperature coefficient 1 ?55 ?5 +40 v/c 100 nf from buf_vref2v5 to agnd4 output impedance 10 t a = 25c load current 1 1.2 ma vdac channel specifications r l = 5 k, c l = 100 pf 3 dc accuracy 1 12 bits 1 lsb = 2.5 v/2 12 resolution 1 12 bits number of data bits relative accuracy 4 inl 4 lsb 1 lsb = 2.5 v/2 12 differential nonlinearity 4 dnl ?0.99 +1 lsb guaranteed monotonic, 1 lsb = 2.5 v/2 12 offset error 3 15 mv 2.5 v internal reference, dac output code 0 drift 13 v/c gain error 5 0.3 0.85 % 0 v to internal v ref range 0.4 1 % 0 v to avdd range drift 6.5 ppm/c excluding reference drift mismatch 0.1 % % of full scale on dac0 analog outputs output voltage range 1 1 0.15 2.5 v output voltage range 2 1 0.15 avddx? 0.15 v output impedance 2 dac ac characteristics output settling time 10 s settled to 1 lsb glitch energy 20 nv-sec 1 lsb change when the maximum number of bits changes simultaneously in the dacxdat register idac channel specifications resolution 1 14 bits combination of overlapping 11 bits and 5 bits full-scale output 1 150 ma supply voltage each channel 1 1.8 2.5 v separate pvddx supply for each channel output compliance range idac0, idac1 0.4 pvddx ? 400 mv v see figure 11 idac2, idac3 0.4 pvddx ? 250 mv v see figure 11
ADUCM320 data sheet rev. c | pa ge 12 of 30 parameter symbol min typ max unit test conditions/comments full - scale error idac set to 85% of full scale idac0, idac1 0.75 % 25c to 105 c range 3.5 % idac2, idac3 0.75 % full - scale error drift idac0, idac1 internal v ref ?40c to 105c 25 a/c 25c to 105c 5 a/c idac2, idac3 2 a/c internal v ref integral nonlinearity inl 3 6 lsb 1 lsb = 150 ma/2 11 differential nonlinearity dnl ?0.99 +1 .5 lsb guaranteed 11 - bit monotonic, 1 lsb = 150 ma/2 11 zero - scale error 50 a zero - scale error drift idac0, idac1 300 na/c idac2, idac3 800 na/c noise current 2 a idacxcon[5:2] = 0 pull - down current ?220 ?165 ?100 a when enabled settling time idacxcon[5:2] = 0 to 0.1% 100 s 4 ma change from midscale to 1% 50 s 4 ma change from midscale full scale to 0 ma 20 s pull - down enabled overheat shutdown 135 c junction temperature pvdd acpsrr idacxcon[5:2] = 0 100 hz 51 db 1 khz 45 db 10 khz 25 db 100 khz 10 db comparator input offset voltage 10 mv bias current 1 na voltage range 1 agndx avddx C 1.2 v capacitance 7 pf hysteresis 1 8.5 15 mv when enabled in software response time 7 s afecomp[2:1] = 0 temperature sensor indicates die temperat ure, see figure 9 resolution 0.5 c when precision calibrated by the user 6 accuracy 1 1.34 1.43 v adc measured voltage for temperature senso r channel without c alibration, t = 25 c power - on reset por 2.85 2.9 v external reset minimum pulse width 1 1.5 s minimum pulse width required on external reset pin to trigger a reset sequence watchdog timer wdt timeout period 32 sec default at power - up flash/ee memory endurance 1 10,000 cycles data retention 1 20 years t j = 85c
data sheet ADUCM320 rev. c | page 13 of 30 parameter symbol min typ max unit test conditions/comments digital inputs input leakage current logic 1 gpio 1 na v ih = v dd , pull - up resistor disabled logic 0 gpio 10 na v il = 0 v, pull - up resistor disabled prtaddrx input leakage current 16 a v in = 0 to 1.8 v, due to weak pull - up resistors to 1.8 v input voltage 0.84 1.5 v external resistor 91 k? 1% to ground, r ange for cfp msa high 1 input capacitance, all pins except mck , mdio , prtaddr x, and xtal x 10 pf input capacitance mck, prtaddrx 6.5 pf m dio 8.5 pf pin capacitance xtali 5 pf xtalo 5 pf logic inputs gpio input voltage low v inl 0.25 iovddx v high v inh 0.58 iovddx v mdio prtaddrx input voltage low v inl 0.36 v high v inh 0.84 v mck, mdio input voltage setup time 10 ns; hold time 10 ns; mck/mdio low v inl 0.36 v high v inh 0.84 v xtali input voltage low v inl 1.1 v high v inh 1.7 v pull - up current 30 120 a v in = 0 v, see figure 10 pul l - down current 30 100 a v in = 3.3 v, see figure 10 logic outputs all digital outputs excluding xtalo gpio output voltage 7 high v oh iovddx ? 0.4 v i source = 2 m a low v ol 0.4 v i sink = 2 ma gp io short - circuit current 1 11 ma see figure 13 mdio output voltage high v oh 1.0 v i source = 4 m a low v ol 0.2 v i sink = 4 m a delay time 10 0 ns mck to mdio out oscillators internal system oscillator 16 mhz accuracy 0.5 3 % system pll 80 mhz main system clock external crystal oscillator 16 mhz can be selected in place of internal oscillator 32 khz internal os cillator 32.768 khz use for watchdog accuracy 5 20 % external clock 0.05 80 mhz can be selected in place of pll start - up time processor clock = 80 mhz at power - on 40 ms por to first user code execution after other reset 1.5 ms res et to first user code execution from all power - down modes 1.25 s
ADUCM320 data sheet rev. c | page 14 of 30 parameter symbol min typ max un it test conditions/comments programmable logic array pla propagation delay pin 17 ns from input pin to output pin element 1.5 ns per pla cell external interrupts pulse width 1 level triggered 7 ns edge triggered 1 ns power requirements 8 power supply voltage range avddx to agndx and iovddx to dgndx 1 2.9 3.3 3.6 v analog power supply currents avddx current 6.3 ma analog peripherals in idle mode digital power supply current iovddx current in normal mode 4 ma all gpio pull-up resistors enabled vddx current normal mode 9 29 ma cd = 0 (80 mhz clock) executing typical code 20 ma cd = 1 executing typical code 10 ma cd = 7 executing typical code core_sleep mode 9 16 ma sys_sleep mode 9 8 ma hibernate mode 9 6.6 ma additional power supply currents adc 4.1 ma continuously converting at 100 ksps adc input buffer 4.0 ma both buffers enabled idac 16.5 ma excluding load current dac 340 a per powered up dac, excluding load current total supply current 35 40 45 ma vdd1, iovddx, avddx connected together; condition when entering user code: peripheral clocks on, peripherals idle, no load currents thermal performance impedance junction to ambient 45 c/w jedec 2s2p 1 these numbers are not production tested but are guaranteed by design and/or characterization data at production release. 2 enabling the input buffer changes the adc input characteristics as described in this subsection. 3 the data in this section a lso applies for a load of r l = 1 k and c l = 100 pf to gnd but only for 0 v to 2.5 v. however, this is not production tested. 4 dac linearity is calcul ated using a reduced co de range of 100 to 3900. 5 dac gain error is calculated using a reduced code range of 100 to an internal 2.5 v v ref . 6 due to self heating, internal temperature measurements cannot be used to predict external temperatures. this value is only relevant after user calibration and only for internal and external conditions identical to those at calibration. 7 the average current from all gpio pins must not exceed 3 ma per pin. 8 power figures exclude any load cu rrents to external circuits. 9 see the ADUCM320 reference manual, how to set up and use the ADUCM320
data sheet ADUCM320 rev. c | page 15 of 30 timing specification s i 2 c timing table 3 . i 2 c timing in standard mode (100 khz) slave parameter description min typ max unit t l scl low pulse width 4.7 s t h scl high pulse width 4.0 ns t shd start condition hold time 4.0 s t dsu data setup time 250 ns t dhd data hold time (sda held internally for 300 n s after falling edge of scl) 0 3.45 s t rsu setup time for repeated start 4.7 s t psu stop conditi on setup time 4.0 s t buf bus - free time between a stop condition and a start condition 4.7 s t r rise time for both s lc and sda 1 s t f fall time for both sl c and sda 15 300 ns t vd;dat data valid time 3.45 s t vd;ack data valid acknowledge ti me 3.45 s table 4 . i 2 c timing in fast mode (400 khz) slave parameter description min typ max unit t l scl low pulse width 1.3 s t h scl high pulse width 0.6 ns t shd start condition hold time 0. 3 s t dsu data setup time 100 ns t dhd data hold time (sda held internally for 300 n s after falling edge of scl) 0 s t rsu setup time for repeated start 0.6 s t psu stop condition setup time 0. 3 s t buf bus - free time between a stop condition and a start condition 1 . 3 s t r rise time for both scl and sda 20 300 ns t f fall time for both scl and sda 15 300 ns t vd;dat data valid time 0.9 s t vd;ack data valid acknowledge time 0.9 s figure 2. i 2 c compatible interface timing 12272-002 sd a (i/o) msb lsb ack msb 1 9 8 2?7 1 sc l (i) p s start condition repeated start stop condition s(r) t dsu t h t l t shd t psu t dsu t buf t dhd t vd; dat t vd; ack t r t f t f t r t dhd t rsu
ADUCM320 data sheet rev. c | pa ge 16 of 30 spi timing table 5 . spi master mode timing (phase mode = 1) parameter description min typ max unit t sl sclk low pulse width (spidiv + 1) t hclk / 2 ns t sh sclk high pulse width (spidiv + 1) t hclk / 2 ns t dav data output valid after sclk edge 0 3 ns t dsu data input setup time before sclk edge ? sclk ns t dhd data input hold time after sclk edge sclk ns t df data output fall time sclk ns t dr data output rise time 25 ns t sr sclk rise time 25 ns t sf sclk fall time 20 ns figure 3. spi master mode timing (phase mode = 1) 12727-003 sclk (polarity = 0) sclk (polarity = 1) mosi msb bits 6 to 1 lsb miso msb in bits 6 to 1 lsb in t sh t sl t sr t sf t dr t df t dav t dsu t dhd
data sheet ADUCM320 rev. c | page 17 of 30 t able 6 . spi master mode timing (phase mode = 0) parameter description min typ max unit t sl sclk low pulse width (spidiv + 1) t hclk / 2 ns t sh sclk high pulse width (spidiv + 1) t hclk / 2 ns t dav data output valid after sclk edge 0 3 ns t dosu data output setup before sclk edge ? sclk ns t dsu data input setup time before sclk edge sclk ns t dhd data input hold time after sclk edge sclk ns t df data output fall time 25 ns t dr data output rise time 25 ns t sr sclk rise time 20 ns t sf sclk fall time 20 ns figure 4 . spi master mode timing (phase mode = 0) 12272-004 sclk (polarity = 0) sclk (polarity = 1) t sh t sl t sr t sf mosi msb bits 6 to 1 lsb miso msb in bits 6 to 1 lsb in t dr t df t dav t dosu t dsu t dhd
ADUCM320 data sheet rev. c | pa ge 18 of 30 table 7 . spi slave mode timing (phase mode = 1) parameter description min typ max unit t cs cs to sclk edge 10 ns t cs m cs high time between active periods scl kx ns t sl sclk low pulse width (spidiv + 1) t hclk ns t sh sclk high pulse width (spidiv + 1) t hclk ns t dav data output valid after sclk edge 20 ns t dsu data input setup time before sclk edge 10 ns t dhd data input hold time after sclk edge 10 ns t df data output fall time 25 ns t dr data output rise time 25 ns t sr sclk rise time 1 ns t sf sclk fall time 1 ns t sfs cs high after sclk edge 20 ns figure 5 . spi slave mode timing (ph ase mode = 1) 12272-005 sclk (polarity = 0) sclk (polarity = 1) t sh t sl t sr t sf t sfs miso msb bits 6 to 1 lsb mosi msb in bits 6 to 1 lsb in t dhd t dsu t dav t dr t df cs t cs t csm
data sheet ADUCM320 rev. c | page 19 of 30 table 8 . spi slave mode timing (phase mode = 0) parameter description min typ max unit t cs cs to sclk edge 10 ns t cs m cs high time between active periods sclkx ns t sl sclk low pulse width (spidiv + 1) t hclk ns t sh sclk high pulse width (spidiv + 1) t hclk ns t dav data output valid after sclk edge 20 ns t dsu data input setup time before sclk edge 10 ns t dhd data input hold time after sclk edge 10 ns t df data output fall time 25 ns t dr data output rise time 25 ns t sr sclk rise time 1 ns t sf sclk fall time 1 ns t docs data output valid after cs edge 20 ns t sfs cs high after sclk edge 10 ns figure 6 . spi slave mode timing (phase mode = 0) 12272-006 sclk (polarity = 0) cs sclk (polarity = 1) t sh t sl t sr t sf t sfs miso mosi msb in bits 6 to 1 lsb in t dhd t dsu msb bits 6 to 1 lsb t docs t dav t dr t df t cs t csm
ADUCM320 data sheet rev. c | pa ge 20 of 30 t able 9 . mdio vs mdc timing parameter description min typ max unit t setup mdio setup before mck edge 10 ns t hold mdio valid after mck edge 10 ns t delay data output after mck edge 100 ns figure 7. mdio timing 12272-007 mck vih vil vih vil voh vol cfp input mdio cfp input mdio cfp output t setup t hold t delay
data sheet ADUCM320 rev. c | page 21 of 30 absol ute maximum ratings all requirements appli cable to each pin must be met. where multiple limits apply to a pin each one m ust be met individually. the limits apply according to the functionality of the pins at the time. pin s that can be either analog or digital, that is, that have two types indi cated in the pin descriptions, must meet the limits for both types. for pin types , see table 11. when powered up , it is required that all ground pins plus adc _ refn be connected together to a node referred to as gnd in table 10. the limits that are listed must be reduced by an y difference between any gnds. also , it is required that avdd3 is connected to avdd4 and that iovdd1 to iovdd3 are connected together . table 10. absolute maximum ratings parameter rating any pin to gnd ? 0.3 v to + 3.9 v any pvddx pin to gnd ?0.3 v to +2.8 v mdio 1 , mck , and prtaddr0 - 4 in mdio mode to gnd ? 0.3 v to +2.1 v between a ny of avddx, iovdd x , and vdd1 pins ? 0.3 v to + 0.3 v any type i p in to gnd 2 ? 0.3 v to iovdd x + 0.3 v any type ai or ao p in to gnd 3 ? 0.3 v to avdd x + 0.3 v any idac x , cdamp x , idactst, iref to gnd ? 0.3 v to pvdd x + 0.3 v adc _ refp to gnd ? 0.3 v to avdd x + 0.3 v total p ositive gpio pin currents 0 ma to 30 ma total n egative gpio pin currents ? 30 ma to 0 ma maximum power dissipation 1 w operating ambient temperature range ? 40c to + 105c storage t emperature range ? 65c to + 160 c operating junction temperature range ? 40c to + 120 c esd hbm 2 kv esd ficdm 1 kv 1 note this pin is always in mdio mode. 2 this limit does not apply i f no current can be drawn b y external circuits on iovddx because then iovdd follows to a suitable level. 3 this limit does not apply if no current can be drawn by external circuits on avddx because then avdd follows to a suitable level. stresses at or above those listed under absolute maximum ratings may c ause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum ope rating conditions for extended periods may affect product reliability. esd caution
ADUCM320 data sheet rev. c | pa ge 22 of 30 pin configuration an d function descripti ons figure 8 . pin configuration table 11 . pin function description s pi n no. mnemonic type 1 description b 2 reset i reset input (active low). an internal pull - up resistor is included. c 2 p 0.0 /sclk 0 /plai[ 0 ] i/o digital i / o port 0.0 (p 0.0 ). spi 0 clock (sclk 0 ). input to pla element 0 (plai[ 0 ]). d 2 p0. 1 /miso 0 /plai[ 1 ] i/o digital i / o port 0.1 (p 0.1 ). spi 0 master in, slave out (miso 0 ). input to pla element 1 (plai[ 1 ]). d 1 p 0.2 /mosi 0 /plai[ 2 ] i/o digital i / o port 0.2 (p 0.2 ). spi 0 master out, slave in (mosi 0 ). input to pla element 2 (plai[2] ). e 3 p 0.3 /irq 0 /cs 0 /placlk 0 /plai[ 3 ] i/o digital i / o port 0.3 (p 0.3 ). external inter r upt 0 (irq 0 ). spi0 chip select 0 (cs0) . when using spi0 , configure this pin as cs 0 . pla clock 0 (placlk 0 ). input to pla element 3 (plai[ 3 ]). e 2 p0.4/scl0/ plao[ 2 ] i/o digital i / o port 0.4 (p 0.4 ). i 2 c 0 serial clock (scl 0 ). output of pla element 2 (plao[ 2 ]). e 1 p 0.5 /sda 0 /plao[ 3 ] i/o digital i / o port 0.5 (p 0.5 ). i 2 c 0 serial data (sda 0 ). output of pla element 3 (plao[ 3 ]). 1 a b c d e f g h j k l 2 3 4 5 6 7 8 9 10 1 1 idac_ tst idac0 idac2 iovdd1 iognd1 p3.3/ pr t addr3/ plai[15] p0.0/ sclk0/ plai[0] cdamp0 cdamp2 cdamp3 cdamp1 idac1 iref idac3 pgnd dgnd2 swclk ain15/ p4.7 ain14/ p4.6 ain12/ p4.4 ain 1 1/ buf_ vref2v5 ain10 ain7 ain2 ain1 ain0 agnd1 vdac4 vdac7/ p5.2 vdac6/ p5.1 x t ali iovdd3 iognd3 vdac3/ p5.0 vdac1 vdd1 a vdd3 agnd2 agnd3 ain3 ain4 ain6 ain5 ain9/ p4.3 ain8/ p4.2 vdac0/ p5.3 vdac2/ p3.7/ plao[29] vdac5 dgnd1 agnd4 ain13/ p4.5 a vdd4 swdio iognd2 iovdd2 pgnd pvdd0 pvdd2 pvdd3 pvdd1 reset 12272-008 p1.0/sin/ eclkin/ plai[4] p1.2/ pwm0/ plai[6] p1.1/sout/ placlk1/ plai[5] p2.4/irq5/ adcconv/ pwm6/ plao[18] p1.3/ pwm1/ plai[7] p1.4/ pwm2/ sclk1/ plao[10] p1.5/ pwm3/ miso1/ plao[ 1 1] p1.6/ pwm4/ mosi1/ plao[12] p1.7/irq1/ pwm5/ cs1/ plao[13] p2.0/irq2/ pwmtrip/ placlk2/ plai[8] p2.2/ irq4/por/ clkout/ plai[10] p2.3/bm p0.2/ mosi0/ plai[2] p0.5/ sda0/ plao[3] p2.6/ irq7/ plao[20] p0.7/ sda1/ plao[5] p0.6/ scl1/ plao[4] p3.0/ pr t addr0/ plai[12] p3.1/ pr t addr1/ plai[13] p2.7/ irq8/ plao[21] p3.5/ mck/ plao[27] x t alo mdio p0.4/ scl0/ plao[2] p0.3/ irq0/cs0/ placlk0/ plai[3] p0.1/ miso0/ plai[1] p3.2/ pr t addr2/ plai[14] p3.4/ pr t addr4/ plao[26] a vdd_ reg0 a vdd_ reg1 vref_1v2 adc_ ref p adc_ refn dvdd_ 2v5 dvdd_1v8 ADUCM320 top view (not to scale)
data sheet ADUCM320 rev. c | page 23 of 30 pi n no. mnemonic type 1 description f 3 p 0.6 /scl 1 /plao[ 4 ] i /o digital i / o port 0.6 (p0.6) . i 2 c1 serial clock (scl1) . output of pla element 4 (plao[4]) . f 2 p 0.7 /sda 1 /plao[ 5 ] i/o digital i / o port 0.7 (p0.7) . i 2 c1 serial data (sda1) . output of pla element 5 (plao[5]) . b 9 p1.0/ sin/eclkin/plai[ 4 ] i/o digital i / o port 1.0 (p1.0) . uart i nput (sin) . external input clock (eclkin) . input to pla element 4 (plai[4]) . b 10 p1.1/sout/placlk1/ plai[ 5 ] i/o digital i / o port 1.1 (p1.1) . uart output (sout) pla clock 1(placlk1) . input to pla el ement 5 (plai[5]) . b 11 p1.2/pwm0/ plai[ 6 ] i/o digital i / o port 1.2 (p1.2) . pwm output 0 (pwm0) . input to pla element 6 (plai[6]) . c 6 p 1.3 /pwm 1 /plai[ 7 ] i/o digital i / o port 1.3 (p1.3) . pwm output 1 (pwm1) . input to pla element 7 (plai[7]) . c 7 p 1.4 /pwm 2 /sclk 1 /plao[ 10 ] i/o digital i / o port 1.4 (p1.4) . pwm output 2 (pwm2) . spi1 c lock (sclk1) . output of pla element 10 (plao[10]) . c 8 p 1.5 /pwm 3 /miso 1 /plao[ 11] i/o digital i / o port 1.5 (p1.5) . pwm output 3 (pwm3) . spi1 master in , slave out (miso1) . output of pla element 11 (plao[11]) . c 9 p 1.6 /pwm 4 /mosi 1 /plao[ 12] i/o digital i / o port 1.6 (p1.6) . pwm output 4 (pwm4) . spi1 master out , slave input (mosi1) . output of pla e lement 12 (plao[12]) . c 10 p1.7/irq1/pwm5/cs 1 /plao[ 13 ] i/o digital i / o port 1.7 (p1.7) . external inter r upt 1 (irq1) . pwm output 5 (pwm5) . spi1 chip select 1 (cs1) . when using spi1, configure this pin as cs1 . output of pla element 13 (plao[13]) . c 5 p 2.0 /irq 2 /pwmtrip/placlk 2 /plai[ 8 ] i /o digital i / o port 2.0 (p2.0) . external inter r upt 2 (irq2) . pwm trip (pwmtrip) . pla input clock 2 (placlk2) . input to pla element 8 (plai[8]) . c 4 p2.2/irq4/ por /clkout /plai[10] i/o digital i / o port 2.2 (p2.2) . extern al inter r upt 4 (irq4) . reset out put ( por ) . this pin function is an output and it is the d efault for pin c4. clock output ( clkout) . input to pla element 10 (plai[10]) . c 3 p 2.3 /bm i/o digital i/o port 2.3 (p2.3) . boot mode (bm). this pin determines the start - up sequence after every reset. pull - up is enabled at power - up.
ADUCM320 data sheet rev. c | pa ge 24 of 30 pi n no. mnemonic type 1 description d 9 p 2.4 /irq 5 /adcconv/pwm 6 /plao[ 18] i/o digital i/o port 2.4 (p2.4) . external inter r upt 5 (irq5) . external i nput to s tart adc c onversions (adcconv) . pwm output 6 (pwm6) . output of pla element 18 (pla o [18]) . f 1 p 2.6 /irq 7 /plao[ 20 ] i/o digital i/o port 2.6 (p2.6) . external inter r upt 7 (irq7) . output of pla element 20 (pla o [20]) . g 1 p 2.7 /irq 8 /plao[ 21 ] i/o digital i/o port 2.7 (p2.7) . external inter r upt 8 (irq8) . output of pla element 21 (pla o [21]) . g 3 p 3.0 /prtaddr 0 /plai[ 12 ] i/o digital i/o port 3.0 (p3.0) . mdio port address bit 0 (prtaddr0). see the digital inputs parameter in table 1 for details. input to pla element 12 (plai[12]) . g 2 p 3.1 /prtaddr 1 /plai[ 13 ] i/o digital i/o port 3.1 (p3.1) . mdio port address bit 1 (prtaddr1) . see the digital inputs parameter in table 1 for details. input to pla element 13 (plai[13]) . d 3 p 3.2 /prtaddr 2 /plai[ 14 ] i/o digital i/o port 3.2 (p3.2) . mdio port address bit 2 (prtaddr2) . see the digital inputs parameter in table 1 for details. input to pla elem ent 14 (plai[14]) . b 3 p 3.3 /prtaddr 3 /plai[ 15 ] i/o digital i/o port 3.3 (p3.3) . mdio port address bit 3 (prtaddr3) . see the digital inputs parameter in table 1 for details. output of pla element 15 (plai[15] ) . c 11 p 3.4 /prtaddr 4 /plao[ 26] i/o digital i/o port 3.4 (p3.4) . mdio port address bit 4 (prtaddr4) . see the digital inputs parameter in table 1 for details. output of pla element 26 (plao[26]) . h 1 p3.5/mck /plao[ 27] i/o digital i/o port 3.5 (p3.5) . mdio clock (mck) see the digital inputs parameter in table 1 for more details. output of pla element 27 (plao[27]) . h 3 mdio i/o mdio data . e 9 swclk i serial wire debug c lock. e 10 swdio i/o serial wire bidirectional data . f 11 vref_ 1 v 2 s 1.2 v reference. this pin c annot be used to source current externally. connect vref_1v2 to agnd x via a 470 nf cap acitor . a 11 iref ai idac r eference c urrent. this pin g enerates the refere nce current for the idacs and is s et by an external resistor , r ext . connect r ext from iref to agnd4. j 6 ain 0 ai analog input 0 . j 7 ain 1 ai analog input 1 . j 8 ain 2 ai analog input 2 . k 8 ain 3 ai analog input 3 . l 8 ain 4 ai analog inpu t 4 . l 9 ain 5 ai analog input 5. ain5 c an be the ? ve input for the comparator. k 9 ain 6 ai analog input 6. ain6 is also the +ve input for the comparator. j 9 ain 7 ai analog input 7. l 10 ain 8 /p 4.2 ai/i/o analog input 8 (ain8) . digital i/o port 4.2 (p4 . 2 ). k 10 ain 9 /p 4.3 ai/i/o analog input 9 (ain9) . digital i/o port 4.3 (p 4.3 ). j 10 ain 10 ai analog input 10 .
data sheet ADUCM320 rev. c | page 25 of 30 pi n no. mnemonic type 1 description j 11 ain 11 /buf_vref2 v 5 ai/ao analog input 11 (ain11) . buffered 2.5 v b ias ( buf_vref2v5 ) . the max imum load = 1.2 ma. connect buf_vref2v5 to agnd x via a 100 nf cap acitor. h 10 ain 12/p 4.4 ai/i/o analog input 12 (ain12) . digital i/o port 4.4 (p4.4) . g 10 ain 13/p 4.5 ai/i/o analog input 13 (ain13) . digital i/o port 4.5 (p4.5) . h 9 ain 14 /p 4.6 ai/i/o analog input 14 (ain14) . digital i/o port 4.6 (p4.6) . g 9 ain 15/p 4.7 ai/i/o analog input 15 (ain15) . digital i/o port 4.7 (p4.7) . l 5 vdac 0 /p 5.3 ao/i/o voltage dac 0 output (vdac0). digital i/o port 5.3 (p5.3) . k 5 vdac 1 ao voltage dac 1 output . l 4 vdac 2 /p 3.7 /plao[ 29] ao/i/o voltage da c 2 output (vdac2). digital i/o port 3.7 (p3.7) . output of pla element 29 (plao[29]) . k 4 vdac 3 /p 5.0 ao/ i/o voltage dac 3 output (vdac3) . digital i/o port 5.0 (p5.0) . j 4 vdac 4 ao v oltage dac 4 output (vdac4). l 3 vdac 5 ao v oltage dac5 output (vda c5). k 3 vdac 6 /p 5.1 ao/i/o v oltage dac 6 output (vdac6). digital i/o port 5.1 (p5.1) . j 3 vdac 7 /p 5.2 ao/i/o voltage dac 7 output (vdac7) . digital i/o port 5.2 (p5.2) . a 2 idac 0 ao idac0. 0 ma to 150 ma full - scale output . a 3 pvdd 0 s power for idac0 . b 4 cdamp 0 ai damping capacitor 0. connect damping capacitor from this pin to pvdd 0 . a 10 idac 1 ao idac1 . 0 ma to 150 ma full - scale output. a 9 pvdd 1 s power for idac1 . b 8 cdamp 1 ai damping capacitor 1. connect damping capacitor from this pin to pvdd 1 . a 5 idac 2 ao idac2 . 0 ma to 150 ma full - scale output. a 4 pvdd 2 s power for idac2 . b 5 cdamp 2 ai damping capacitor 2. connect damping capacitor from this pin to pvdd 2 . a 7 idac 3 ao ida3c . 0 ma to 150 ma full - scale output. a 8 pvdd 3 s power for idac3 . b 7 cda mp 3 ai damping capacitor 3. connect damping capacitor from this pin to pvdd 3 . b 6 pgnd s power supply ground for idacs. a 6 pgnd s power supply ground for idacs . a 1 idac_tst ai/ao pin for idac test purposes. leave idac_tst unconnected. l 2 dvdd_ 1 v 8 ao 1.8 v digital supply. a 470 nf capacitor to dgnd1 must be connected to this pin to stabili z e the internal 1.8 v regulator that supplies flash memory and the arm cortex -m 3 processor. k 2 dvdd_ 2 v 5 ao 2.5 v digital supply. a 470 nf capacitor to iognd3 must be co nnected to this pin to stabili z e the internal 2.5 v regulator that supplies the analog digital control. f 9 avdd_reg 0 ao analog regulator 0 supply. a 470 nf capacitor to agnd4 must be connected to this pin to stabili z e the internal 2.5 v regulator that sup plies the adc. f 10 avdd_reg 1 ao analog regulator 1 supply. output of 2.5 v on - chip ldo regulator. a 470 nf capacitor to agnd 4 must be connected to this pin. this regulator supplies the idacs. l 1 dgnd 1 s digital ground 1 for dvdd_ 1 v 8 . d 10 dgnd 2 s digita l ground 2 . connect to dgnd 1 . b 1 iovdd 1 s 3.3 v gpio supply.
ADUCM320 data sheet rev. c | pa ge 26 of 30 pi n no. mnemonic type 1 description d 11 iovdd 2 s 3.3 v gpio supply and interdie communications . j 1 iovdd 3 s 3.3 v gpio supply. c 1 iognd 1 s ground for iovdd1 . e 11 iognd 2 s ground for iovdd2 . k 1 iognd 3 s ground for iovdd3 and i nterdie communications . j 5 agnd 1 s analog g round for vdd1 . k 7 agnd 2 s esd ground for p ad r ing. l 7 agnd 3 s ground for avdd3 . h 11 agnd 4 s ground for avdd4, avdd_reg0 , and avdd_reg 1 . k 6 vdd 1 s 3.3 v supply for digital die . l 6 avdd 3 s vdac and idac supp ly (3.3 v) . g 11 avdd 4 s adc supply (3.3 v) . l 11 adc_refn ao/a decoupling capacitor connection for adc reference buffer . connect this pin to agnd 4 . k 11 adc_refp ao/a decoupling capacitor connection for adc reference buffer . connect this pin to a 4.7 f capacitor to the adc_refn pin. adc_refp can be overdriven by an external reference. h 2 xtalo o output from the crystal oscillator inverter. when not using an external crystal , leave xtalo unconnected. j 2 xtali i input to the crystal oscillator inverter a nd input to the internal clock generator circuits. when not using an external crystal , connect xtali to dgnd. 1 ai is analog input, a o is analog output , i is digital input, o is digital output, s is supply .
data sheet ADUCM320 rev. c | page 27 of 30 typical performance characteristics figure 9. typical temperature measurement vs. internal temperature (v dd = 3.3 v, 50 ksps) figure 10 . typical pull - up/pull - down pin current vs. pin voltage (v dd = 3.3 v, 25 c) figure 11 . typical idac headroom vs. idac output current figure 12 . t ypical pvdd ac psrr vs. frequency figure 13 . typical output voltage vs. load current figure 14 . vdd1 power - on requirements 25000 30000 35000 40000 45000 50000 ?60 ?40 ?20 0 20 40 60 80 100 120 adc code (lsb 16) temper a ture (c) device 1 device 2 device 3 device 4 device 5 12272-009 ?10 0 10 20 30 40 50 60 70 80 90 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 pin current (a) pin vo lt age (v) max pul l u p min pul l u p min pulldown max pulldown 12272-010 0 50 100 150 200 250 300 350 0 25 50 75 100 125 150 idac headroom (mv) idac output current (ma) idac 2 idac 3 idac 0 idac 1 12272-0 1 1 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 100 1k 10k 100k pvdd ac psrr (db) frequenc y (hz) idac0 idac1 idac2 idac3 12272-012 0 0.5 1.0 1.5 2.0 2.5 3.0 2 6 10 14 16 0 4 8 12 output vo lt age (v) load current (ma) 12272-013 v oh max v oh min v ol min v ol max time (not to scale) 3.60 50ms min vdd1 (v) dvdd must be above 2.9v for at least 50ms to complete por after 50ms dvdd must stay above 2.85v including noise excursions 2.90 2.85 12272-014
ADUCM320 data sheet rev. c | pa ge 28 of 30 recommended c ircuit and c omponent v alues fig ure 15 shows a typical connection diagram for the ADUCM320 . supplies and regulators must be adequately decoupled with capacitors connected between the avddx, pvddx, dvdd_x, avdd_regx, iovddx , and vdd1 balls and their associated gnd balls (agndx, pgnd, iogndx, and dgndx ). table 11 indicates which ground balls are paired with which supply balls. there are four digital supply balls, iovdd1, iovdd2, iovd d3, and vdd 1 . decouple these balls with a 100 nf capacitor placed as near as possible to each of the four balls and their associated gnd balls (iogndx and agnd 1 , respectively). in addition, place a 10 f capacitor conveniently near to these balls. similar ly, the analog supply pins, avdd 3 and av dd 4 , each require a 100 nf capacitor placed as near as possible to each ball and its associated agndx ball, and place a 10 f capacitor conveniently near to these balls. the idacs source their output currents from th e pvddx supply balls. each pvddx supply ball must have a 100 nf capacitor near to each ball and their associated gnd balls (pgnd). in addition, place at least one 10 f capacitor at the source of the pvddx supply. the idac output filters depend on a 10 nf capacitor being placed between the cdampx and pvddx. the adc reference requires a 4.7 f capacitor placed between adc_refp and adc_refn and located as near as possible to each ball. adc_refn must be connected directly to agnd 4 . the ADUCM320 contains four internal regulators. these regulators require external decoupling capacitors. the dvdd_1v8 and dvdd_2v5 balls each require a 470 nf capacitor to dgnd1 and iognd3, respectively. avdd_reg0 and av dd_reg 1 each require a decoupling capacitor to agnd 4 . to generate an accurate and low drift reference current, connect the iref ball to agnd4 via a low ppm 3.16 k? resistor. take care in the layout to ensure that currents flowing from the ground end of each decoupling capacitor to its associated ground ball share as little track as possible with other ground currents on the printed circuit boar d.
data sheet ADUCM320 rev. c | page 29 of 30 figure 15 . recommended circuit and component values g11 l6 b6 pgnd reset reset adc_refp gnd dgnd swdio tx swclk avdd avdd3 avdd4 vref_1v2 iref adc_refn a vdd_reg0 avdd_reg1 agnd1 agnd3 agnd2 f9 l11 k11 a11 f11 h11 l7 k7 j5 f10 agnd4 3.16k ? 0.47f 4.7f 0.47f 0.47f b2 c1 e11 p1.1/sout j2 swdio h2 a3 a9 12pf 10nf a6 pgnd l1 d10 ADUCM320 cdamp2 cdamp1 cdamp0 pvdd3 pvdd2 pvdd1 pvdd0 xtalo xtali reset reset a4 a8 b4 b8 b5 vdd1 cdamp3 b7 swclk p1.0/sin/eclkin/plai[4] p2.3/bm k1 iovdd1 iovdd3 iovdd2 vdd1 dvdd_1v8 dvdd_2v5 dgnd1 dgnd2 iognd1 iognd2 iognd3 10k ? pvdd 10nf 10nf 10nf dvdd vdd1 0.47f 0.47f vdd1 10k ? 10f 10f 0.1f 10k? 1.6? vin vout en gnd dgnd avdd dvdd agnd agnd 0.1f 10f adp7102ardz3.3 0.1f v in sense0 pg 0.1f 1.6? vdd1 dgnd dgnd1 10f vin vout en gnd adp1741acpz ss ep 10f 30k? 10k? 10f +2.5v 10f adj pvdd 12pf pgnd pgnd pgnd dgnd nc dvdd agnd 0.1f agnd1 l2 k6 j1 d11 b1 k2 e10 b10 e9 b9 c3 12272-015 interface board connector rx
ADUCM320 data sheet rev. c | pa ge 30 of 30 packaging and ordering information outline dimensions figure 16 . 96 - ball chip scale package ball grid array [csp_bga] (bc - 96 - 2) dimensions sho wn in millimeters ordering guide model 1 temperature range package description package option ordering quantity ad u cm 320 bbcz ?40c to +10 5 c 96 - ball chip scale package ball grid array [csp_bga] bc - 96 - 2 429 adu cm320bbcz -rl ?40c to +10 5 c 96 - ball chip scale package ball grid array [csp_bga] bc -96 -2 2 , 500 ev - aducm 320 qspz evaluation board with quickstart development system 1 1 z = rohs compliant part. i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). 6.10 6.00 sq 5.90 5.00 ref sq 0.35 0.30 0.25 04-02-2013- a coplanarit y 0.08 a b c d e f g h j k l 7 6 3 2 1 5 4 ball diameter 0.50 bsc 0.50 ref de t ai l a a1 ball corner a1 ball corner detail a bottom view top view seating plane 1.200 1.083 1.000 8 9 10 11 compliant t o jedec s t andards mo-195-ac with the exception to ball count. 0.223 nom 0.173 min 0.93 0.86 0.79 ? 2014 C 2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d12272 - 0 - 10/15(c) ww w.analog.com/ ADUCM320

▲Up To Search▲

Price & Availability of ADUCM320

	To Download ADUCM320 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .